Radiation Hardened Mixed-signal Ip with Dare Technology

Recent trends show the growing need for more analog and mixed-signal IP to enhance the intelligence and reduce the cost of satellites. This paper presents the current state of the imec DARE solution with a focus on the strong increase in mixed-signal and analog IP blocks. In addition, the DARE solution is being extended to high-voltage technology targeting a similar mixed-signal IP offering in a different foundry technology. First the recent improvements and additions to the DARE library are presented. Secondly radiation test results on technology level are presented showing the extensive level of analogue characterization of the DARE solution. The mixed-signal expansion is illustrated with a software controlled SOC ASIC project. This ASIC contains, amongst others, improved, hardened PLL and ADC blocks. These blocks will be discussed together with the under-radiation simulation approach. DARE+ ACTIVITY The Design Against Radiation Effects (DARE) library is being further developed in the ESA activity DARE+. The focus of this follow-up activity is to strengthen the existing, mainly digitally oriented, UMC 180nm based offering and expand it with Mixed-Mode capabilities. Developments are ongoing to add a set of integrated clock gating cells, a Dual Port SRAM Compiler, improve the single event (SE) behavior of the existing Phase Locked Loop (PLL), extend the common mode input range of the available LVDS Receiver and improve the reliability and mixed-mode performance of the IO cells. All the library cells are re-characterized with the Mixed-Mode transistor models. Table 1 lists the DARE+ library activities. DARE+ increases the analog content with a bandgap design and a linear voltage regulator. These analog circuits have been designed up to now with the standard provided transistor models and with the experience of good analog designers. However for advanced high-speed and high-accuracy designs an improved model is required. The Analog Design Kit (ADK) currently models the basic geometry effects of the Enclosed Layout Transistor (ELT), but it’s the goal to also model Total Ionizing Dose (TID) effects for the analog components in the technology and further increase the simulation accuracy of analog transistor parameters. Table 2gives an overview of the selected analog components and the relevant analog parameters that are (possibly) influenced by TID. Radiation tests are scheduled on a Devices Test Vehicle (DTV) that was designed and taped-out in Q1 2012. Transistors for many width and length combinations, with and without ELT geometry, inside or outside triple well, at 1.8V or 3.3V, ... are used in test structures to measure IV-curves, VT-shift, matching, noise under different radiation conditions. The DTV is not intended for SEE measurements. Figure 2 shows the 5mm by 5mm die layout of the DTV. First test results are expected in Q3 2012.